Janusz Biernat, Prof.


Contact:

Office: 201, Building: C-3

Phone: +48 71 320-3916

Fax: +48 71 321-2677 , Office phone: +48 71 320-2745

janusz.biernat@pwr.edu.pl

Janusz Biernat

Janusz Biernat received his Ph.D. degree from Wrocław University of Technology in 1977. Since 1992 he is a professor at Wroclaw University of Technology. His research area include theoretical and practical aspects of reliability, architecture and organisation of computer systems and applications of residue number systems. He is an author of three textbooks (in polish) devoted to computer arithmetic and architecture. 
He is a reviewer in IEEE Transaction on Reliability journal as well as on a number of international conferences focused on dependability and reliability of computer systems.

He is a primary investigator in research project from Polish Ministry of Science and Higher Education focused on Dynamic Thermal Management of Many-Core Microprocessors and Automatic synthesis of high-performance constant-coefficient FIR filters based on Residue Number System arithmetic

Current research projects

  1. Automatic synthesis of high-performance constant-coefficient FIR filters based on residue number system arithmetic
  2. Dynamic Thermal Management in Multi-Core Microprocessors

Past research projects

  1. Negative differential resistance devices and synthesis of logic gates and circuits, 2010-2012
  2. Negative differential resistance devices and synthesis of logic gates, 2008-2010
  3. Countermeasures to fault analysis for cryptographic hardware, 2007-2008
  4. Computer-aided design of digital signal processing datapaths, 2004-2007

Recent publications


Journal Articles

B. Wojciechowski, K. Berezowski, P. Patronik, and J. Biernat : Fast and accurate thermal modeling and simulation of manycore processors and workloads, Microelectronics Journal, vol.44(11), 2013, pp. 986–993, URL, DOI, BibTeX
@ARTICLE{wojciechowski2013fast,
  author = {B. Wojciechowski and K. Berezowski and P. Patronik and J. Biernat},
  title = {{Fast and accurate thermal modeling and simulation of manycore processors and workloads}},
  journal = {{Microelectronics Journal}},
  volume = {44},
  number = {11},
  year = {2013},
  pages = {986–993},
  doi = {10.1016/j.mejo.2012.08.001},
  url = {http://www.sciencedirect.com/science/article/pii/S0026269212001875},
  keywords = {processor thermal characterisation}
}
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M. Nikodem, M. Bawiec, and J. Biernat : Synthesis of generalised threshold gates and multi threshold threshold gates, International Journal of Electronics and Telecommunications, vol.58(1), 2012, pp. 49-54, DOI, BibTeX
@ARTICLE{2012a,
  author = {Maciej Nikodem and Marek Bawiec and Janysz Biernat},
  title = {{Synthesis of generalised threshold gates and multi threshold threshold gates}},
  journal = {{International Journal of Electronics and Telecommunications}},
  volume = {58},
  number = {1},
  year = {2012},
  pages = {49-54},
  doi = {http://dx.doi.org/10.2478/v10177-012-0007-5}
}
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J. Biernat : Fast fault-tolerant adders, International Journal of Critical Computer-Based Systems, vol.1(1), 2010, pp. 117-127, BibTeX
@ARTICLE{biernat2010fast,
  author = {Janusz Biernat},
  title = {{Fast fault-tolerant adders}},
  journal = {{International Journal of Critical Computer-Based Systems}},
  publisher = {{Inderscience}},
  volume = {1},
  number = {1},
  year = {2010},
  pages = {117-127}
}
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J. Biernat : Fast fault-tolerant adders, IJCCBS, vol.1(), 2010, pp. 117-127, BibTeX
@ARTICLE{Biernat2010,
  author = {J. Biernat},
  title = {{Fast fault-tolerant adders}},
  journal = {{IJCCBS}},
  volume = {1},
  number = {1/2/3},
  year = {2010},
  pages = {117-127}
}
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J. Biernat and J. Jabłoński : Minimum logic depth modulo 2^n+1 adders, Metody Informatyki Stosowanej, vol.16(3), 2008, pp. 41-55, BibTeX
@ARTICLE{Biernat2008e,
  author = {J. Biernat and J. Jabłoński},
  title = {{Minimum logic depth modulo 2^n+1 adders}},
  journal = {{Metody Informatyki Stosowanej}},
  volume = {16},
  number = {3},
  year = {2008},
  pages = {41-55}
}
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J. Biernat : The complexity of fault-tolerant adder structures, Dependability of Computer Systems, International Conference on, 2008, pp. 316-323, DOI, BibTeX
@ARTICLE{Biernat2008d,
  author = {J. Biernat},
  title = {{The complexity of fault-tolerant adder structures}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{Dependability of Computer Systems, International Conference on}},
  publisher = {{IEEE Computer Society}},
  volume = {0},
  year = {2008},
  pages = {316-323},
  doi = {10.1109/DepCoS-RELCOMEX.2008.60}
}
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J. Biernat : Tajniki arytmetyki komputerów, Przegląd Telekomunikacyjny, Wiadomości Telekomunikacyjne, vol.81(6), 2008, pp. 759-762, BibTeX
@ARTICLE{Biernat2008,
  author = {J. Biernat},
  title = {{Tajniki arytmetyki komputerów}},
  journal = {{Przegląd Telekomunikacyjny, Wiadomości Telekomunikacyjne}},
  volume = {81},
  number = {6},
  year = {2008},
  pages = {759-762}
}
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J. Biernat, M. Czapski, and M. Nikodem : Error correction procedures for a hardware implementation of the advanced encryption standard, Dependability of Computer Systems, International Conference on, 2006, pp. 307-312, DOI, BibTeX
@ARTICLE{Biernat2006b,
  author = {J. Biernat and M. Czapski and M. Nikodem},
  title = {{Error correction procedures for a hardware implementation of the advanced encryption standard}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{Discrete-Event System Design 2006}},
  publisher = {{University of Zielona G�ra}},
  volume = {0},
  year = {2006},
  pages = {307-312},
  doi = {10.1109/DEPCOS-RELCOMEX.2006.50}
}
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J. Biernat : Self-dual modules in design of dependable digital devices, Dependability of Computer Systems, International Conference on, 2006, pp. 276-281, DOI, BibTeX
@ARTICLE{Biernat2006c,
  author = {J. Biernat},
  title = {{Self-dual modules in design of dependable digital devices}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{Dependability of Computer Systems, International Conference on}},
  publisher = {{IEEE Computer Society}},
  volume = {0},
  year = {2006},
  pages = {276-281},
  doi = {10.1109/DEPCOS-RELCOMEX.2006.50}
}
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Conference Papers

B. Wojciechowski and J. Biernat : Temperature prediction for multi-core microprocessors with application to Dynamic Thermal Management, Thermal Investigations of ICs and Systems (THERMINIC), 2012 18th International Workshop on, 2012, pp. 1-6, BibTeX
@INPROCEEDINGS{6400625,
  author = {B. Wojciechowski and J. Biernat},
  title = {{Temperature prediction for multi-core microprocessors with application to Dynamic Thermal Management}},
  booktitle = {{Thermal Investigations of ICs and Systems (THERMINIC), 2012 18th International Workshop on}},
  month = {Sep},
  year = {2012},
  pages = {1-6},
  keywords = {microprocessor chips, multiprocessing systems, performance evaluation, thermal management (packaging), cpu performance, dynamic thermal management, multicore microprocessors, task migration, temperature prediction, computational modeling}
}
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B. Wojciechowski, K. Berezowski, P. Patronik, and J. Biernat : Fast and accurate thermal simulation and modelling of workloads of many-core processors, Thermal Investigations of ICs and Systems (THERMINIC), 2011 17th International Workshop on, 2012, pp. 1-6, BibTeX
@INPROCEEDINGS{6081029,
  author = {B. Wojciechowski and K. Berezowski and P. Patronik and J. Biernat},
  title = {{Fast and accurate thermal simulation and modelling of workloads of many-core processors}},
  booktitle = {{Thermal Investigations of ICs and Systems (THERMINIC), 2011 17th International Workshop on}},
  month = {Sep},
  year = {2012},
  pages = {1-6},
  keywords = {fourier transforms, multi-threading, multiprocessing systems, thermal analysis, benchmark traces, core thermal status, few-component fourier expansion, many-core processors, multithreaded workload, power consumption, system throughput, thermal simulation, workload modelling, approximation methods, benchmark testing, computational modeling, instruction sets, mathematical model, microprocessors}
}
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M. Wesołowski, P. Patronik, K. Berezowski, and J. Biernat : Design of a Novel Flexible 4-moduli RNS and Reverse Converter, To appear in Proceedings of The 23rd IET Irish Signals and Systems Conference, 2012, BibTeX
@INPROCEEDINGS{Wesolowski2012,
  author = {M. Wesołowski and P. Patronik and K. Berezowski and J. Biernat},
  title = {{Design of a Novel Flexible 4-moduli RNS and Reverse Converter}},
  booktitle = {{To appear in Proceedings of The 23rd IET Irish Signals and Systems Conference}},
  month = {Jun},
  year = {2012},
  keywords = {rns}
}
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P. Patronik, K. Berezowski, J. Biernat, S. Piestrak, and A. Shrivastava : Design of an RNS reverse converter for a new five-moduli special set, ACM Great Lakes Symposium on VLSI, 2012, pp. 67-70, BibTeX
@INPROCEEDINGS{DBLP:conf/glvlsi/PatronikBBPS12,
  author = {P. Patronik and K. Berezowski and J. Biernat and S. Piestrak and A. Shrivastava},
  title = {{Design of an RNS reverse converter for a new five-moduli special set}},
  booktitle = {{ACM Great Lakes Symposium on VLSI}},
  year = {2012},
  pages = {67-70}
}
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M. Nikodem, M. Bawiec, and J. Biernat : Synthesis of Multithreshold Threshold Gates, VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on, 2012, pp. 94-99, BibTeX
@INPROCEEDINGS{nikodem2012synthesis,
  author = {Maciej Nikodem and Marek Bawiec and Janusz Biernat},
  title = {{Synthesis of Multithreshold Threshold Gates}},
  booktitle = {{VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on}},
  year = {2012},
  pages = {94-99}
}
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P. Patronik, K. Berezowski, S. Piestrak, J. Biernat, and A. Shrivastava : Fast and energy-efficient constant-coefficient FIR filters using residue number system, Low Power Electronics and Design (ISLPED) 2011 International Symposium on, 2011, pp. 385-390, BibTeX
@INPROCEEDINGS{patronik2011fast,
  author = {Piotr Patronik and Krzysztof Berezowski and Stanisław Piestrak and Janusz Biernat and Aviral Shrivastava},
  title = {{Fast and energy-efficient constant-coefficient FIR filters using residue number system}},
  booktitle = {{Low Power Electronics and Design (ISLPED) 2011 International Symposium on}},
  year = {2011},
  pages = {385-390}
}
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P. Patronik, K. Berezowski, S. Piestrak, J. Biernat, and A. Shrivastava : Fast and energy-efficient constant-coefficient FIR filters using residue number system, ISLPED, 2011, pp. 385-390, BibTeX
@INPROCEEDINGS{DBLP:conf/islped/PatronikBPBS11,
  author = {P. Patronik and K. Berezowski and S. Piestrak and J. Biernat and A. Shrivastava},
  title = {{Fast and energy-efficient constant-coefficient FIR filters using residue number system}},
  booktitle = {{ISLPED}},
  year = {2011},
  pages = {385-390}
}
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M. Nikodem, M. Bawiec, and J. Biernat : Synthesis of Generalised Threshold Gates and Multi Threshold Threshold Gates, ICSEng, 2011, pp. 463-464, BibTeX
@INPROCEEDINGS{DBLP:conf/icseng/NikodemBB11,
  author = {M. Nikodem and M. Bawiec and J. Biernat},
  title = {{Synthesis of Generalised Threshold Gates and Multi Threshold Threshold Gates}},
  booktitle = {{ICSEng}},
  year = {2011},
  pages = {463-464}
}
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J. Biernat, T. Serafin, and W. Kulikowski : Hardware implementation of the REED-SOLOMON decoder, Intelligent Engineering Systems (INES), 2010 14 extsuperscriptTH International Conference on, 2010, pp. 255-257, BibTeX
@INPROCEEDINGS{biernat2010hardware,
  author = {J Biernat and T Serafin and W Kulikowski},
  title = {{Hardware implementation of the REED-SOLOMON decoder}},
  booktitle = {{Intelligent Engineering Systems (INES), 2010 14	extsuperscriptTH International Conference on}},
  year = {2010},
  pages = {255-257}
}
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J. Biernat : The complexity of fault-tolerant adder structures, Dependability of Computer Systems, 2008. DepCos-RELCOMEX'08. Third International Conference on, 2008, pp. 316-323, BibTeX
@INPROCEEDINGS{biernat2008complexity,
  author = {Janusz Biernat},
  title = {{The complexity of fault-tolerant adder structures}},
  booktitle = {{Dependability of Computer Systems, 2008. DepCos-RELCOMEX'08. Third International Conference on}},
  year = {2008},
  pages = {316-323}
}
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Books

J. Biernat : Architektura układów arytmetyki resztowej, Exit, 2007, BibTeX
@BOOK{Biernat2007a,
  author = {J. Biernat},
  title = {{Architektura układów arytmetyki resztowej}},
  publisher = {{Exit}},
  year = {2007}
}
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J. Biernat : Architektura komputerów, Oficyna Wydaw. PWroc, 2005, BibTeX
@BOOK{Biernat2005e,
  author = {J. Biernat},
  title = {{Architektura komputerów}},
  publisher = {{Oficyna Wydaw. PWroc}},
  year = {2005}
}
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Article in collection

MarekA. Bawiec, B. Wojciechowski, M. Nikodem, and J. Biernat : Synthesis of Logic Circuits Based on Negative Differential Resistance Property, Computer Aided Systems Theory – EUROCAST 2011, Springer Berlin Heidelberg, ISBN: 978-3-642-27548-7, 2012, pp. 505-512, DOI, BibTeX
@INCOLLECTION{raey,
  author = {MarekA. Bawiec and Bartosz Wojciechowski and Maciej Nikodem and Janusz Biernat},
  title = {{Synthesis of Logic Circuits Based on Negative Differential Resistance Property}},
  booktitle = {{Computer Aided Systems Theory – EUROCAST 2011}},
  publisher = {{Springer Berlin Heidelberg}},
  volume = {6927},
  year = {2012},
  isbn = {978-3-642-27548-7},
  pages = {505-512},
  doi = {10.1007/978-3-642-27549-4_65},
  keywords = {nanodevices, negative differential resistance, synthesis}
}
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