Tadeusz Tomczak, Ph. D.


Contact:

Office: 223, Building: C-3

Phone: +48 71 320-2873

Fax: +48 71 321-2677 , Office phone: +48 71 320-2745

tadeusz.tomczak@pwr.wroc.pl

Tadeusz Tomczak

Tadeusz Tomczak received his Ph.D. degree from Wrocław University of Technology where he works as an post-doc researcher in computer science. His research interests include fast computation hardware, parallel computing including massively parallel processors, and computationally intensive algorithms.

He cooperates with Vratis Ltd. as an expert in the field of parallel programming and GPU computing.

His addtional interests include power electronics and renewable energy systems.

 

 

 


Recent publications


Journal Articles

T. Tomczak : Hierarchical residue number systems with small moduli and simple converters, 2011, BibTeX
@ARTICLE{tomczak2011hierarchical,
  author = {Tadeusz Tomczak},
  title = {{Hierarchical residue number systems with small moduli and simple converters}},
  year = {2011}
}
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Z. Malecha, Ł. Mirosław, T. Tomczak, Z. Koza, M. Matyka, W. Tarnawski, D. Szczerba, and et al : GPU-based simulation of 3D blood flow in abdominal aorta using OpenFOAM, Archives of Mechanics, vol.63(2), 2011, pp. 137-161, BibTeX
@ARTICLE{malecha2011gpu,
  author = {Z Malecha and Ł Mirosław and T Tomczak and Z Koza and M Matyka and W Tarnawski and D Szczerba and et al},
  title = {{GPU-based simulation of 3D blood flow in abdominal aorta using OpenFOAM}},
  journal = {{Archives of Mechanics}},
  volume = {63},
  number = {2},
  year = {2011},
  pages = {137-161}
}
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T. Tomczak : Fast Sign Detection for RNS (2n-1,2n,2n+1), Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.55(6), 2008, pp. 1502-1511, DOI, BibTeX
@ARTICLE{Tomczak2008,
  author = {T. Tomczak},
  title = {{Fast Sign Detection for RNS $(2^n-1,2^n,2^n+1)$}},
  journal = {{Circuits and Systems I: Regular Papers, IEEE Transactions on}},
  volume = {55},
  number = {6},
  month = {Jul},
  year = {2008},
  pages = {1502-1511},
  doi = {http://dx.doi.org/10.1109/TCSI.2008.917994}
}
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T. Tomczak : Fast Sign Detection for RNS (2 n-1, 2 n, 2 n+ 1), Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.55(6), 2008, pp. 1502-1511, BibTeX
@ARTICLE{tomczak2008fast,
  author = {Tadeusz Tomczak},
  title = {{Fast Sign Detection for RNS (2 n-1, 2 n, 2 n+ 1)}},
  journal = {{Circuits and Systems I: Regular Papers, IEEE Transactions on}},
  publisher = {{IEEE}},
  volume = {55},
  number = {6},
  year = {2008},
  pages = {1502-1511}
}
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T. Tomczak : Residue arithmetic in FPGA matrices, Dependability of Computer Systems, International Conference on, 2006, pp. 297-305, DOI, BibTeX
@ARTICLE{Tomczak2006c,
  author = {T. Tomczak},
  title = {{Residue arithmetic in FPGA matrices}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{Dependability of Computer Systems, International Conference on}},
  publisher = {{IEEE Computer Society [Press]}},
  volume = {0},
  year = {2006},
  pages = {297-305},
  doi = {http://doi.ieeecomputersociety.org/10.1109/DEPCOS-RELCOMEX.2006.43}
}
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T. Tomczak : Układy arytmetyki resztowej w matrycach FPGA, Pomiary, Automatyka, Kontrola, ISSN: 0032-4110, 2006, pp. 92-94, BibTeX
@ARTICLE{Tomczak2006a,
  author = {T. Tomczak},
  title = {{Układy arytmetyki resztowej w matrycach FPGA}},
  journal = {{Pomiary, Automatyka, Kontrola}},
  number = {nr 7bis wyd. spec. dod.},
  year = {2006},
  issn = {0032-4110},
  pages = {92-94},
  note = {referat z IX konferencji nt. Reprogramowalne układy cyfrowe RUC '06. Szczecin, 18-19.05.2006}
}
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T. Tomczak : Residue arithmetic in FPGA matrices, Dependability of Computer Systems, International Conference on, 2006, pp. 297-305, DOI, BibTeX
@ARTICLE{Tomczak2006,
  author = {T. Tomczak},
  title = {{Residue arithmetic in FPGA matrices}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{Dependability of Computer Systems, International Conference on}},
  publisher = {{IEEE Computer Society [Press]}},
  volume = {0},
  year = {2006},
  pages = {297-305},
  doi = {10.1109/DEPCOS-RELCOMEX.2006.43}
}
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M. Gomulkiewicz, M. Nikodem, and T. Tomczak : Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips, Dependability of Computer Systems, International Conference on, 2006, pp. 282-288, DOI, BibTeX
@ARTICLE{Gomulkiewicz2006,
  author = {M. Gomulkiewicz and M. Nikodem and T. Tomczak},
  title = {{Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips}},
  journal = {{Dependability of Computer Systems, International Conference on}},
  booktitle = {{DepCoS-RELCOMEX}},
  volume = {0},
  year = {2006},
  pages = {282-288},
  doi = {http://doi.ieeecomputersociety.org/10.1109/DEPCOS-RELCOMEX.2006.36}
}
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Conference Papers

T. Tomczak : Metody i układy sprzętowego wspomagania obliczeń w algorytmach oświetlenia globalnego, Reprogramowalne układy cyfrowe. RUC 2005. Materiały VIII krajowej konferencji naukowej, Szczecin : Instytut Informatyki PSzczec., 2005, pp. 139-148, BibTeX
@INPROCEEDINGS{Tomczak2005a,
  author = {T. Tomczak},
  title = {{Metody i układy sprzętowego wspomagania obliczeń w algorytmach oświetlenia globalnego}},
  booktitle = {{Reprogramowalne układy cyfrowe. RUC 2005. Materiały VIII krajowej konferencji naukowej}},
  publisher = {{Szczecin : Instytut Informatyki PSzczec.}},
  year = {2005},
  pages = {139-148}
}
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T. Tomczak : Hierarchiczne resztowe systemy liczbowe w strukturach FPGA, Inżynieria komputerowa, Wydawnictwa Komunikacji i Łączności, 2005, pp. 405-414, BibTeX
@INPROCEEDINGS{Tomczak2005,
  author = {T. Tomczak},
  title = {{Hierarchiczne resztowe systemy liczbowe w strukturach FPGA}},
  booktitle = {{Inżynieria komputerowa}},
  publisher = {{Wydawnictwa Komunikacji i Łączności}},
  year = {2005},
  pages = {405-414}
}
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