Conference Papers

S. Leshner, K. Berezowski, X. Yao, G. Chalivendra, S. Patel, and S. Vrudhula : A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS, ISVLSI, 2010, pp. 210-215, BibTeX
@INPROCEEDINGS{DBLP:conf/isvlsi/LeshnerBYCPV10,
  author = {S. Leshner and K. Berezowski and X. Yao and G. Chalivendra and S. Patel and S. Vrudhula},
  title = {{A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS}},
  booktitle = {{ISVLSI}},
  year = {2010},
  pages = {210-215}
}
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