Journal Articles

T. Gowda, S. Vrudhula, N. Kulkarni, and K. Berezowski : Identification of Threshold Functions and Synthesis of Threshold Networks, IEEE Trans. on CAD of Integrated Circuits and Systems, vol.30(5), 2011, pp. 665-677, BibTeX
@ARTICLE{DBLP:journals/tcad/GowdaVKB11,
  author = {T. Gowda and S. Vrudhula and N. Kulkarni and K. Berezowski},
  title = {{Identification of Threshold Functions and Synthesis of Threshold Networks}},
  journal = {{IEEE Trans. on CAD of Integrated Circuits and Systems}},
  volume = {30},
  number = {5},
  year = {2011},
  pages = {665-677}
}
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K. Berezowski and S. Vrudhula : Multiple-valued logic circuits design using negative differential resistance devices, Journal of Multiple-Valued Logic and Soft Computing, vol.13(), 2007, pp. 447-466, BibTeX
@ARTICLE{2007a,
  author = {Krzysztof Berezowski and Sarma Vrudhula},
  title = {{Multiple-valued logic circuits design using negative differential resistance devices}},
  journal = {{Journal of Multiple-Valued Logic and Soft Computing}},
  volume = {13},
  number = {4-6},
  year = {2007},
  pages = {447-466}
}
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Conference Papers

S. Leshner, N. Kulkarni, S. Vrudhula, and K. Berezowski : Design of a robust, high performance standard cell threshold logic family for DSM technology, Microelectronics (ICM), 2010 International Conference on, 2010, pp. 52-55, BibTeX
@INPROCEEDINGS{leshner2010design,
  author = {Samuel Leshner and Niranjan Kulkarni and Sarma Vrudhula and Krzysztof Berezowski},
  title = {{Design of a robust, high performance standard cell threshold logic family for DSM technology}},
  booktitle = {{Microelectronics (ICM), 2010 International Conference on}},
  year = {2010},
  pages = {52-55}
}
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S. Leshner, K. Berezowski, X. Yao, G. Chalivendra, S. Patel, and S. Vrudhula : A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS, ISVLSI, 2010, pp. 210-215, BibTeX
@INPROCEEDINGS{DBLP:conf/isvlsi/LeshnerBYCPV10,
  author = {S. Leshner and K. Berezowski and X. Yao and G. Chalivendra and S. Patel and S. Vrudhula},
  title = {{A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS}},
  booktitle = {{ISVLSI}},
  year = {2010},
  pages = {210-215}
}
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R. Rao, S. Vrudhula, and K. Berezowski : Analytical results for design space exploration of multi-core processors employing thread migration, Proceedings of the 13 extsuperscriptTH international symposium on Low power electronics and design, 2008, pp. 229-232, BibTeX
@INPROCEEDINGS{rao2008analytical,
  author = {Ravishankar Rao and Sarma Vrudhula and Krzysztof Berezowski},
  title = {{Analytical results for design space exploration of multi-core processors employing thread migration}},
  booktitle = {{Proceedings of the 13	extsuperscriptTH international symposium on Low power electronics and design}},
  year = {2008},
  pages = {229-232}
}
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K. Berezowski and S. Vrudhula : Multiple-valued logic circuits design using negative differential resistance devices, Multiple-Valued Logic, 2007. ISMVL 2007. 37 extsuperscriptTH International Symposium on, 2007, pp. 24-24, BibTeX
@INPROCEEDINGS{berezowski2007multiple,
  author = {Krzysztof Berezowski and Sarma Vrudhula},
  title = {{Multiple-valued logic circuits design using negative differential resistance devices}},
  booktitle = {{Multiple-Valued Logic, 2007. ISMVL 2007. 37	extsuperscriptTH International Symposium on}},
  year = {2007},
  pages = {24-24}
}
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